Two Cache Computer

 

Two Cache Computer

Introducing a new computer architecture. 

Current computers talk, cache coherence. The new design has cache synergy.

There are different types of software data. Computer hardware treats all data as one.

It can only be faster to treat data with two different algorithms.

Introducing a new instruction that enables two types of data processing.

Like wing flaps that optimize airflow, a Two Cache Computer has coherent cache synergy. 

The program selects the cache which determines the processing methodology.

 

The first result is revolutionary. Then step two makes one cache vanish.

Processors can then be connected solely to the memory bus.

The new computer design runs any current multitasking computer software.

The computer is fully described in the Journal of Computer Science and Technology.

Offering a $1 million dollar prize

(Must precede and is contingent upon a licensing agreement.)

Coherent Main Memory

Different Algorithms for the Same Problem

Software has Three Data Types

Three Data Types

 Software recognizes three types of data

But hardware can not differentiate. 

Idea 1 -  Create Data Type Allocation Instruction

 

Idea 2 - Store Data in one place

1970 - Relational Data Bases

 

Idea 3 - Serialize updates through one instruction

1973 - Conditional compare and swap (CS)

 

Combine the three ideas:

Allocation instruction enables hardware to protect update integrity in three ways.

Exclusive data is not shared and can reside in a cache.

Shared data is updated in one place and CS protects using a pointer swap or lock.

Swap data is handled with an atomic CS. (pointer swap, lock, counter)

The hardware no longer needs to ensure update integrity because the software protects with a CS.  Because data is stored in one place.

 

However:

CS was implemented in the cache and with coherence (1965 algorithm).

Solution:

Perform the CS in one place which for multi-core is main memory.

Result:

Coherence vanishes because the software provides update integrity.

Scalable processors that connect only to the bus.

These multi-core processors can either reduce the multitasking queue or 

run a dedicated process or both.

 

 Different Algorithms for the Same Problem

 

 

 

 

History of Coherence 

1965 - Multiprocessor buffer interrogation*

1970 - Relational DB

1973 - Compare and Swap (CS)

Late 1970s - Locks replaced by CS

1980s - Invalidation replaces Interrogation (Snoopy*)

2022 - Patent for CS in main memory. (CS & main memory)

2023 - Patent for Coherent Memory. (Relational & main memory)

2023 - Patent to identify memory that needs to be coherent. (1970 & 1973 & 2022)

202? - Coherence vanishes.

 

Relational main memory does not require coherence.

 It is Coherent Memory

Coherent Memory = Relational Memory = Shared Data = Relational Data

 

 * Uses an algorithm that is binomial and limits multi core to 4. 

 

 Different Algorithms for the Same Problem

 

 

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Different Algorithms for the Same Problem