Coherent Main Memory

The Journal of Computer Science and Technology March 2024 article CFP: A Coherence-Free Processor Design explains reducing coherence in two steps, and the second step is 100%. 

Keywords: multiprocessor, multitasking, cache, coherence, snoopy, atomic

 

Overview -  Different Algorithms for the same Problem

Technical Explanation - An Alternative to Coherence

 

 

Prior Start Points

Introducing Thread-safe Computers

Software is Coherence-Free - Multitasking Software is already Coherence-Free. Cache coherence has not been redesigned despite two software innovations.

Coherent Memory maintains main memory data integrity without cache coherence.

Coherent Memory organizes main memory. - Database managers organize data for performance. Computers should organize memory too. Software already does. Hardware needs more information.

Coherent Memory enables Parallel Cores to Share Coherent Memory. This is true parallel processing. 

 

Algorithm:

coming soon - Coherence is Binomial - Because multiprocessor cores must talk to maintain synchronization, the overhead for adding cores is binomial. This is explained by the Birthday Problem.

Two Step Algorithm for Coherence Reduction - If data is not shared with another task, it does not require coherence. Currently the hardware does not know whether data is shared.

Two Cache Computer - Explanation of the system as a Two Cache Processor.

Coherent Memory Management - Software self-protects without coherence.

coming soon - CFPs connect to the Memory Bus - CFPs do not talk, so they can connect to the main memory bus. It enables attaching devices that contain a CFP. 

Parallel AI Processing - A computer with parallel cores can process multiple AI prompts simultaneously. Current computers can not efficiently add cores.

Ethical AI Paradox - Ownership creates a Conflict Of Interest. CFP royalties can fund a COI-free open source Ethical AI System owned by We The People and modified by vote.

Draft for wiki - Need assistance due to COI.

WIPO Patent 1 - WIPO patent for Independent Processor Caches in a Scalable Multiprocessor System Absent a Hardware Cache Coherence Protocol. (WO2024076380)

coming soon - WIPO Patent 2 - WIPO patent for Method, System, and Computer Program Product for Allocating an Exclusive Memory Resource. (PCT/US24/27631)

submitted - Multiple Core Computing - A less technical but more detailed explanation of the Coherence-Free Processor. It is intended to be understood by anyone with a BS in Computer Science.