Introducing Thread-safe Computers

(Peer reviewed and published here) 

 

Thread-safe computers run multiple threads simultaneously and in parallel with no data races.

Software is already thread-safe since it is re-entrant.
However current multi-core processors require coherence or invalidation.

These methods limit the number of threads executed simultaneously in a system.

Simultaneous execution requires one core per thread. 

Insufficient cores generate concurrency which is multitasking.

Using thread-safe core processors eliminates both coherence and invalidation.

Using thread-safe core processors permits sufficient cores to eliminate concurrency.

Concurrency is reduced by delegating to another core. 

Concurrency increases elapsed time, though not execution time. 

The thread-safe algorithm has two major steps.

Step 1:

Allocate private data in a coherent thread-safe cache. The entire cache is coherent.

The result is less coherence, even without step 2. This is because current computers require 

coherence on all data. Implementation requires a new allocation instruction.

Step 2:

Modify the atomic instruction (i.e., compare and swap or cmpxchg) which updates shared 

memory to be thread-safe. (Current implementation requires coherence.)

Thread-safe core processors synchronize hardware updates using this thread-safe atomic 

instruction for physical update integrity.

Therefore a thread-safe computer has hardware update integrity, whereas existing computers 

require coherence to provide hardware update integrity.

Current software’s thread-safe logic works for a thread-safe computer. (The software is 

thread-safe.)

Therefore a thread-safe computer has both physical hardware update integrity and logical 

software update integrity.

Step 2 summary - A thread-safe computer uses atomic instructions modified to be thread-safe 

and therefore implemented without coherence. This eliminates the current limit on the number 

of core processors in a system.

Needed:

I am in need of a writer to explain the impact of the first architectural change to 

multitasking computers in the last 60 years.

It is essential for AI because it permits multiple simultaneous processes.

In current architecture, coherence limits the number of cores thus limiting the number of 

simultaneous threads. 

Keywords

Multiprocessor, Multitasking, Thread-safe, Cache, Coherence, Atomic, Snoopy

Journal of Computer Science and Technology article

Draft for wiki (not an entry due to COI)

Other explanations (blog)

Frank Yang

FrankYang43338@acm.org

Different Algorithms for the Same Problem